Field of the Invention
The present invention relates to a digital phase-locked loop. It particularly relates to a digital phase-locked loop in which a random walk filter is used to effectively suppress the jitter of an input signal.
BACKGROUND OF THE INVENTION
A conventional digital phase-locked loop has been used for many purposes such as signal retiming and signal selection (refer to "IEEE Transactions on Communications", vol. COM-20, No. 2, page 95, April, 1972: Title: Phase Noise and Transient times for a Binary Quantized Digital Phase-Locked Loop in White Gaussian Noise, written by JAMES R. CESSNA, DONALD M. LEVY). In the conventional digital phase-locked loop shown in FIG. 1, an input digital signal to the system and the output signal of a scaler 25 are supplied to a binary phase detector 21. The output of the binary phase detector 21 is a lead output or a lag output and is selectively supplied to a random walk filter 22. An advance input or a retard input is sent from the random walk filter 22 to a phase controller 14. An oscillator 23 supplies to the phase controller 24a signal whose frequency is much higher than that of the input digital signal. The output of the phase controller 24 is frequency-divided by the scaler 25, the output of which is sent to the outside of the digital phase-locked loop as well as fed back to the binary phase detector 21.
As shown in FIG. 2, the major part of the random walk filter 22 is an up-down counter 22a having 2N stages. The count of the counter 22a is increased by one every time the lead input is supplied thereto. The count of the counter 22a is decreased by one every time the lag input is supplied thereto. The carry output of the updown counter 22a is used as the advance output. The borrow output of the counter 22a is used as the retard output. The output signal of an OR gate 22b, which receives both the outputs, is supplied to the resetting terminal of the up-down counter 22a to reset the count of the counter to N.
When the lead input has been supplied a number of times, which is N more than that of the supply of the lag input, the advance output is sent out from the up-down counter 22a for the phase controller 24 to delay the phase of the output of the stable fixed oscillator 23. Thereafter, the scaler 25 frequency divides the phase delayed signal to send out a signal compensated for the phase deviation.
When the lag input has been supplied a number of times N more than that for which the lead input has been supplied, the retard output is sent out from the up-down counter 22a to advance the phase of the output of the stable fixed oscillator 23 by the phase controller 24. The phase advanced output is frequency divided by the scaler 25 to send out a signal compensated for the phase deviation.
As understood from the above description, the control of the phase is not necessarily performed immediately after the supply of the lead input or the lag input but is performed only when the number of times of the supply of one of the lead input and the lag input has become N more than that of times of the supply of the other. As a result, the jitter of the input digital signal can be suppressed to stabilize the phase of the output signal.
In the above-described conventional digital phase-locked loop, the effect of the jitter suppression can be enhanced by increasing the number of the stages of the up-down counter 22a. However, if the number of the stages of the up-down counter 22a is increased, the response time of the digital phase-locked loop is lengthened in proportion to the increased number of the stages so that the effect of the jitter suppression and the transient characteristic of the loop conflict with each other. In other words, the transient characteristic is degraded if the effect of the jitter suppression is enhanced and the effect of the jitter suppression is degraded if the transient characteristic is enhanced.